In order to avoid damage to electronic circuits during electrostatic discharge (ESD) protection circuits have been devised to shunt current to ground and limit exposure to excessive voltages. A variety of devices have been developed including grounded gate NMOS, LVTSCR, and BJT triggering clamps. BJTs typically rely on avalanche breakdown and may be enhanced through the use of zener diodes to trigger the base of the BJT. These triggering clamps typically have relatively small dimensions with an active device width of 100-500 mm. However, they typically have high-triggering voltage levels and display breakdown characteristics that are process sensitive and in most cases, result in degradation, especially after exposure to multiple ESD pulses.
Normal operation mode clamps such as Merrill clamps are also known. These differ from triggering clamps insofar as they do not rely on avalanche injection conductivity modulation, but instead make use of a driver to be switched on. These CMOS normal operating mode clamps display large dimensions of the order of 10-20 mm since they have to deal with normal operating conditions where the current density is much lower. They find use in power devices, involving a whole chip design approach with rail protection strategies and wide metal buses where the increase in size due to the space consuming devices is less significant. On the other hand, they have the benefit of displaying excellent ESD protection characteristics.
A particular problem experienced by triggering clamps is so-called hot carrier degradation (HCD) and soft leakage. HCD has been ascribed to post-ESD stress caused by residual high voltage levels after triggering off. These residual high voltage levels approximately equal the triggering or breakdown voltage of the triggering structure. In the case of low leakage circuits, these voltage levels may be stored for a long time thereby causing long term overload, causing HCD of the gate oxide.
Examples of the prior art triggering clamps are illustrated in FIGS. 1-4 where FIG. 1 shows a grounded gate NMOS (GGNMOS) device 10 in which the gate is connected to ground via a resistor 12. FIG. 2 makes use of a low voltage triggering silicon controlled rectifier (LVTSCR) 20. FIG. 3 shows the use of a NPN BJT 30 that makes use of avalanche breakdown to provide ESD protection. FIG. 4 also makes use of an NPN transistor 40, but is supplemented with a zener diode 42 which feeds base current into the NPN transistor 40. All of these triggering circuits make use of snapback characteristics of the devices.
The present invention seeks to address the problem of HCD and soft leakage increase displayed by triggering clamps due to multiple ESD spikes.